(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method that provides added and improved control over the profile of gate spacers that are created over sidewalls of a gate electrode.
(2) Description of the Prior Art
Presently existing CMOS technology is based on the creation of Field Effect Transistors (FET) over active surface regions of a silicon substrate, the created FET devices are electrically isolated by regions of isolation such as Shallow Trench Isolation regions. Creating Field Effect Transistor devices typically comprises creating regions of controlled conductivity in the surface of a substrate that are aligned with the gate electrode. Recognized in the creation of FET devices are first the creation of a layer of gate oxide over the surface of the substrate, a layer of gate material, typically comprising polysilicon, is deposited over the layer of gate oxide. Both layers of gate material and gate oxide are patterned and etched, creating the body of the gate electrode. Next and self-aligned with the body of the gate electrode, lightly doped impurity implantations are performed into the surface of the substrate, creating lightly doped diffusion (LDD) regions in the surface of the substrate for improved hot electron flow adjacent to the body of the gate electrode. Gate spacers are then formed over sidewalls of the body of the gate electrode after which source and drain impurity implantations are performed self-aligned with the body and the gate spacers of the gate electrode. Improved contact resistance can be achieved by saliciding the contact surfaces of the gate electrode, that is the surface of the source/drain regions and the top surface of the gate material. After the optional salicidation process has been completed, conductive contact plugs are established to the contact surfaces of the gate electrode through a layer of dielectric that is deposited over the surface of the substrate, thereby including the exposed surfaces of the created gate electrode.
Improved semiconductor device performance has over the years been provided by reducing device dimensions, thereby reducing the paths that need to be traveled by electron charges in addition to reducing such factors are resistive loss and parasitic influences that have a negative impact on device operational speed and functional performance. This continued reduction in the elements that collectively form an operational semiconductor device has imposed on the art of creating semiconductor devices increased demands of accuracy and control in creating the devices. A small deviation from a desired device element has a relative larger impact on the device performance if the small deviation constitutes a relative larger percentage of the design parameters of that device element. The invention specifically addresses the creation of gate spacers over sidewalls of the body of the gate electrode. In prior art applications of creating spacers for gate electrodes, the layer of gate material and gate oxide are etched by first creating a patterned and etched layer of hard mask material over these layers. The hard mask pattern protects the layers of gate material and gate oxide in a pattern of the body of the gate electrode. The problem that is encountered in etching the layers of gate material and gate oxide in this manner is that an overetch occurs into the surface of the isolation material that has been used to fill the STI trenches. This overetch typically occurs in the perimeter of the isolation material, where this isolation material interfaces with the surrounding silicon of the substrate. As a consequence, divots appear in the perimeter of the surface of the isolation material. The pattern of hard mask material is removed, a layer of gate spacer material is deposited over the surface of the patterned gate material and etched to create the gate spacers. Residue of gate spacer material will have been accumulated in the divots in the surface of the STI regions, this residue material must be removed, which causes loss of the now exposed layer of gate material. Complete removal of the gate spacer material from the divots in the STI surface is required for reasons of leakage currents and voltage isolation requirements. This complete removal of the accumulated gate spacer material however typically results in an excessive amount of loss of the exposed layer of gate material, making salicidation of the layer of gate material very problematic. The invention provides a method whereby this problem of accumulation of gate spacer material in divots in the surface of the isolation material in the STI trenches is prevented.
U.S. Pat. No. 5,923,991 (Bronner et al.) shows a process to prevent divots in the surface of the isolation material of STI trenches.
U.S. Pat. No. 5,741,738 (Mandelman et al.) shows a process to protect the surface of STI regions.
U.S. Pat. No. 6,207,513 (Vollrath) shows a spacer process to eliminate corner device in STI regions.
A principle objective of the invention is to create gate spacers over the sidewalls of patterned and etched layers of gate material such that the gate material is not excessively removed.
In accordance with the objectives of the invention a new process is provided for the creation of an improved gate spacer profile. A layer of hardmask material is patterned over the surface of a layer of gate material. The layer of gate material is etch in accordance with the patterned layer of hardmask material, reducing the thickness of the patterned layer of hardmask material. A liner oxide is formed, a film of gate spacer material is deposited over the liner material. The layer of spacer material is etched, forming gate spacers and at the same time the remaining layer of hardmask material.